Inventor · Santa Clara, CA, US

Mehdi Saremi

2Patents
0h-index
14Co-inventors
28Inventor score

Filing activity: Aug 24, 2020 → Dec 17, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US11699755B2 Stress incorporation in semiconductor devices Electricity 0 Active
US12356665B2 Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.