Stress incorporation in semiconductor devices
US11699755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2020 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Aug 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/796
Abstract
Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.