Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods
US12356665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2021 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jul 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.