Mohan R. Nagar
12Patents
4h-index
11Co-inventors
53Inventor score
Filing activity: Jan 23, 2002 → Oct 12, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7641776B2 | System and method for increasing yield from semiconductor wafer electroplating | Electricity | 45 | Active |
| US6825556B2 | Integrated circuit package design with non-orthogonal die cut out | Electricity | 10 | Expired |
| US6605954B1 | Reducing probe card substrate warpage | Physics | 7 | Expired |
| US8736044B2 | Lid for an electrical hardware component | Emerging Cross-Sectional Technologies | 4 | Active |
| US9320183B1 | Ground lid opening on a substrate | Electricity | 3 | Active |
| US8952523B2 | Integrated circuit package lid configured for package coplanarity | Emerging Cross-Sectional Technologies | 3 | Active |
| US7352062B2 | Integrated circuit package design | Electricity | 3 | Expired |
| US6946866B2 | Measurement of package interconnect impedance using tester and supporting tester | Physics | 2 | Expired |
| US8962388B2 | Method and apparatus for supporting a computer chip on a printed circuit board assembly | Emerging Cross-Sectional Technologies | 1 | Active |
| US6717423B1 | Substrate impedance measurement | Physics | 1 | Expired |
| US6891392B2 | Substrate impedance measurement | Physics | 1 | Expired |
| US8081484B2 | Method and apparatus for supporting a computer chip on a printed circuit board assembly | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.