Measurement of package interconnect impedance using tester and supporting tester
US6946866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2003 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.