Naoki Ookuma
9Patents
3h-index
12Co-inventors
50Inventor score
Filing activity: Oct 26, 2010 → Nov 13, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10734080B2 | Three-dimensional memory device containing bit line switches | Physics | 8 | Active |
| US10854619B2 | Three-dimensional memory device containing bit line switches | Electricity | 8 | Active |
| US9852078B2 | Data mapping for non-volatile storage | Physics | 4 | Active |
| US8526229B2 | Semiconductor memory device | Physics | 2 | Active |
| US11081192B2 | Memory plane structure for ultra-low read latency applications in non-volatile memories | Physics | 0 | Active |
| US10984874B1 | Differential dbus scheme for low-latency random read for NAND memories | Electricity | 0 | Active |
| US10885984B1 | Area effective erase voltage isolation in NAND memory | Physics | 0 | Active |
| US8284598B2 | Semiconductor memory device | Physics | 0 | Active |
| US11177277B2 | Word line architecture for three dimensional NAND flash memory | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.