Memory plane structure for ultra-low read latency applications in non-volatile memories
US11081192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Oct 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.