Area effective erase voltage isolation in NAND memory
US10885984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Oct 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.