List insertion in test segments with non-naturally aligned data boundaries
US11094391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Sep 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.