Riccardo Gemelli
17Patents
6h-index
20Co-inventors
66Inventor score
Filing activity: Jul 30, 1999 → May 22, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9154446B2 | Device and method for switching data traffic in a digital transmission network | Electricity | 75 | Active |
| US6970966B2 | System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol | Physics | 37 | Expired |
| US7082563B2 | Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets | Electricity | 27 | Expired |
| US7130942B2 | Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding | Physics | 20 | Expired |
| US8594136B2 | Transmission of parallel data flows on a parallel bus | Electricity | 10 | Active |
| US7289502B1 | Method and device for routing or compressing packets destination address containing classless address | Electricity | 10 | Expired |
| US6549536B1 | Method of address compression for cell-based and packet-based protocols and hardware implementations thereof | Electricity | 5 | Expired |
| US6964574B2 | Daughter board for a prototyping system | Physics | 4 | Expired |
| US9203725B2 | Update of a cumulative residence time of a packet in a packet-switched communication network | Electricity | 3 | Active |
| US7036095B2 | Clock generation system for a prototyping apparatus | Physics | 2 | Expired |
| US11055173B2 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Physics | 1 | Active |
| US10528422B2 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Physics | 0 | Active |
| US8429511B2 | Equipment protection method and apparatus | Electricity | 0 | Active |
| US11463720B2 | Functional safety method, system, and corresponding computer program product | Electricity | 0 | Active |
| US11436162B2 | Functional safety method, corresponding system-on-chip, device and vehicle | Physics | 0 | Active |
| US10860415B2 | Memory architecture including response manager for error correction circuit | Electricity | 0 | Active |
| US10379937B2 | Memory architecture including response manager for error correction circuit | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.