Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
US11055173B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 4, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Dec 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.