Memory architecture including response manager for error correction circuit
US10379937B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.