Rich Klein
14Patents
11h-index
16Co-inventors
65Inventor score
Filing activity: Oct 9, 1990 → Apr 25, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5614765A | Self aligned via dual damascene | Electricity | 125 | Expired |
| US5705430A | Dual damascene with a sacrificial via fill | Electricity | 113 | Expired |
| US5795823A | Self aligned via dual damascene | Electricity | 79 | Expired |
| US5686354A | Dual damascene with a protective mask for via etching | Electricity | 63 | Expired |
| US5691238A | Subtractive dual damascene | Electricity | 57 | Expired |
| US5691573A | Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines | Electricity | 39 | Expired |
| US5776834A | Bias plasma deposition for selective low dielectric insulation | Electricity | 27 | Expired |
| USD333731S | Tie rack | General | 17 | Expired |
| US5955786A | Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines | Electricity | 17 | Expired |
| US6051882A | Subtractive dual damascene semiconductor device | Electricity | 13 | Expired |
| US6048802A | Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines | Electricity | 11 | Expired |
| US5990557A | Bias plasma deposition for selective low dielectric insulation | Electricity | 10 | Expired |
| US6287953A | Minimizing transistor size in integrated circuits | Electricity | 9 | Expired |
| US7026691B1 | Minimizing transistor size in integrated circuits | Electricity | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.