Minimizing transistor size in integrated circuits
US6287953A · kind A · utility
9Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.