Minimizing transistor size in integrated circuits
US7026691B1 · kind B1 · utility
5Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2001 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Mar 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.