Distributed read and write caching implementation for optimized input/output applications
US6681292B2 · kind B2 · utility
179Cited by
10References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 27, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.