Scott Janus
74Patents
9h-index
152Co-inventors
81Inventor score
Filing activity: Jan 10, 2000 → May 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11113784B2 | Sparse optimizations for a matrix accelerator architecture | Physics | 36 | Active |
| US11620256B2 | Systems and methods for improving cache efficiency and utilization | Physics | 32 | Active |
| US7647557B2 | Techniques for shuffling video information | Electricity | 25 | Active |
| US10699465B1 | Cluster of scalar engines to accelerate intersection in leaf node | Physics | 19 | Active |
| US10846814B2 | Patch processing mechanism | Electricity | 16 | Active |
| US10893299B2 | Surface normal vector processing mechanism | Physics | 15 | Active |
| US7345689B2 | Interfacing a digital display card through PCI express connector | Physics | 14 | Expired |
| US10911799B2 | Video refinement mechanism | Physics | 13 | Active |
| US11049266B2 | Point cloud viewpoint and scalable compression/decompression | Physics | 9 | Active |
| US7568980B1 | Natural surface golf mat | Fixed Constructions | 9 | Active |
| US9253524B2 | Selective post-processing of decoded video frames based on focus point determination | Electricity | 8 | Active |
| US6707853B1 | Interface for performing motion compensation | Electricity | 6 | Expired |
| US7825915B2 | Codec control | Physics | 5 | Active |
| US11145105B2 | Multi-tile graphics processor rendering | Physics | 4 | Active |
| US12079155B2 | Graphics processor operation scheduling for deterministic latency | Physics | 4 | Active |
| US7219170B2 | Burst transfer register arrangement | Physics | 4 | Expired |
| US9531916B2 | Preventing pattern recognition in electronic code book encryption | Electricity | 4 | Active |
| US11284118B2 | Surface normal vector processing mechanism | Physics | 4 | Active |
| US11676239B2 | Sparse optimizations for a matrix accelerator architecture | Physics | 4 | Active |
| US8237695B2 | Codec control | Physics | 3 | Active |
| US11018863B2 | Graphics processor with encrypted kernels | Physics | 3 | Active |
| US10367639B2 | Graphics processor with encrypted kernels | Physics | 3 | Active |
| US9519803B2 | Secure environment for graphics processing units | Physics | 3 | Active |
| US11861761B2 | Graphics processing unit processing and caching improvements | Emerging Cross-Sectional Technologies | 3 | Active |
| US10909039B2 | Data prefetching for graphics data processing | Emerging Cross-Sectional Technologies | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.