Patent · US Active

Graphics processor operation scheduling for deterministic latency

US12079155B2 · kind B2 · utility

4Cited by

88References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Joydeep Ray · Folsom, US
Selvakumar Panneer · Portland, US
Saurabh Tangri · Folsom, US
Ben J. Ashbaugh · Folsom, US
Scott Janus · Rocklin, US
Abhishek R. Appu · Cameron Park, US
Varghese George · Folsom, US
Ravishankar Iyer · Portland, US
Nilesh Jain · Portland, US
Pattabhiraman K · Bengaluru, IN
Altug Koker · Cameron Park, US
Mike B. Macpherson · Portland, US
Josh B. Mastronarde · Sacramento, US
Elmoustapha Ould-Ahmed-Vall · Chandler, US
Jayakrishna P S · Bengaluru, IN
Eric C. Samson · Folsom, US

Key dates

Filing date	Mar 14, 2020
Grant date	Sep 3, 2024
Priority date	—
Expiry date	Sep 15, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.