Systems and methods for improving cache efficiency and utilization

US11620256B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Altug Koker · Cameron Park, US
• Joydeep Ray · Folsom, US
• Ben J. Ashbaugh · Folsom, US
• Jonathan Pearce · Hillsboro, US
• Abhishek R. Appu · Cameron Park, US
• Vasanth Ranganathan · Cameron Park, US
• Lakshminarayanan Striramassarma · Folsom, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Aravindh Anantaraman · Folsom, US
• Valentin Andrei · San Jose, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Varghese George · Folsom, US
• Yoav Harel · Folsom, US
• Arthur Hunter · Cameron Park, US
• Brent Insko · Portland, US
• Scott Janus · Rocklin, US
• Pattabhiraman K · Bengaluru, IN
• Mike B. Macpherson · Portland, US
• Subramaniam Maiyuran · Citrus, US
• Marian Alin Petre · San Mateo, US
• Murali Ramadoss · Folsom, US
• Shailesh Shah · San Jose, US
• Kamal Sinha · Rancho Cordova, US
• Prasoonkumar Surti · Folsom, US
• Vikranth Vemulapalli · Folsom, US

Key dates

• Filing date: Apr 28, 2022
• Grant date: Apr 4, 2023
• Expiry date: Apr 28, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.