Shankarnarayan Bhat
2Patents
1h-index
10Co-inventors
34Inventor score
Filing activity: Apr 1, 2015 → Apr 25, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9711241B2 | Method and apparatus for optimized memory test status detection and debug | Physics | 1 | Active |
| US9972402B2 | Continuous write and read operations for memories with latencies | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.