Patent · US Active

Continuous write and read operations for memories with latencies

US9972402B2 · kind B2 · utility

0Cited by

11References

13Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Nishi Bhushan Singh · Bengaluru, IN
Ashutosh Anand · Nagamangala, IN
Anand Bhat · Bengaluru, IN
Rajesh Tiwari · Plano, US
Shankarnarayan Bhat · Bengaluru, IN

Key dates

Filing date	Apr 25, 2016
Grant date	May 15, 2018
Priority date	—
Expiry date	Jun 8, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0401
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.