Patent · US Active

Method and apparatus for optimized memory test status detection and debug

US9711241B2 · kind B2 · utility

1Cited by

4References

18Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Ashutosh Anand · Nagamangala, IN
Shankarnarayan Bhat · Bengaluru, IN
Nikhil Sudhakaran · Bengaluru, IN
Praveen Raghuraman · Chennai, IN
Nishi Bhushan Singh · Bengaluru, IN
Anand Bhat · Bengaluru, IN
Abhinav Kothiala · Bengaluru, IN
Sanjay Muchini · Bengaluru, IN
Arun Balachandar · Bengaluru, IN
Devadatta Bhat · Bengaluru, IN

Key dates

Filing date	Apr 1, 2015
Grant date	Jul 18, 2017
Priority date	—
Expiry date	Jun 19, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/1208
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.