Inventor · Boise, ID, US

Thy Tran

4Patents
2h-index
8Co-inventors
37Inventor score

Filing activity: Mar 10, 2010 → Oct 14, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8716116B2 Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline Electricity 23 Active
US9613864B2 Low capacitance interconnect structures and associated systems and methods Electricity 2 Active
US12272167B2 Systems and methods for automated acceptance of form documents Physics 0 Active
US9911653B2 Low capacitance interconnect structures and associated systems and methods Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.