Patent · US Active

Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline

US8716116B2 · kind B2 · utility

23Cited by
8References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 10, 2010
Grant dateMay 6, 2014
Priority date
Expiry dateJul 31, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B12/482

Abstract

A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.