Low capacitance interconnect structures and associated systems and methods
US9613864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.