Veit Gernhoefer
4Patents
2h-index
16Co-inventors
37Inventor score
Filing activity: Dec 1, 2004 → Sep 20, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7315994B2 | Method and device for automated layer generation for double-gate FinFET designs | Electricity | 167 | Expired |
| US7568173B2 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration | Physics | 3 | Active |
| US7865848B2 | Layout optimization using parameterized cells | Physics | 2 | Active |
| US8448124B2 | Post timing layout modification for performance | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.