Patent · US Active

Post timing layout modification for performance

US8448124B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Uwe Fassnacht · Sunnyvale, US
Veit Gernhoefer · Holzgerlingen, DE
Michael S. Gray · Saint Albans, US
Joachim Keinert · Altdorf, DE

Key dates

Filing date	Sep 20, 2011
Grant date	May 21, 2013
Priority date	—
Expiry date	Sep 20, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.