Patent · US Expired

Method and device for automated layer generation for double-gate FinFET designs

US7315994B2 · kind B2 · utility

167Cited by

5References

8Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ingo Aller · Holzgerlingen, DE
Veit Gernhoefer · Holzgerlingen, DE
Joachim Keinert · Altdorf, DE
Thomas Ludwig · Sindelfingen, DE

Key dates

Filing date	Dec 1, 2004
Grant date	Jan 1, 2008
Priority date	—
Expiry date	Sep 20, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.