Die stack address bus having a programmable width
US10002653B2 · kind B2 · utility
0Cited by
24References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.