Vertical FET structure

US10002962B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent A. Anderson · Jericho, US
• Huiming Bu · Millwood, US
• Fee Li Lie · Albany, US
• Edward J. Nowak · South Burlington, US
• Junli Wang · Slingerlands, US

Key dates

• Filing date: Apr 27, 2016
• Grant date: Jun 19, 2018
• Expiry date: Apr 27, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.