Inventor · Albany, NY, US

Fee Li Lie

173Patents
12h-index
109Co-inventors
85Inventor score

Filing activity: Jun 18, 2014 → Mar 21, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9608065B1 Air gap spacer for metal gates Electricity 89 Active
US9620590B1 Nanosheet channel-to-source and drain isolation Electricity 86 Active
US9805935B2 Bottom source/drain silicidation for vertical field-effect transistor (FET) Electricity 27 Active
US9748380B1 Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure Physics 25 Active
US9799765B1 Formation of a bottom source-drain for vertical field-effect transistors Electricity 25 Active
US9362179B1 Method to form dual channel semiconductor material fins Electricity 24 Active
US9472506B2 Registration mark formation during sidewall image transfer process Electricity 22 Active
US9842931B1 Self-aligned shallow trench isolation and doping for vertical fin transistors Electricity 21 Active
US9754798B1 Hybridization fin reveal for uniform fin reveal depth across different fin pitches Electricity 13 Active
US9305845B2 Self-aligned quadruple patterning process Emerging Cross-Sectional Technologies 13 Active
US9450095B1 Single spacer for complementary metal oxide semiconductor process flow Electricity 13 Active
US10553522B1 Semiconductor microcooler Electricity 12 Active
US9853127B1 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Electricity 12 Active
US10002962B2 Vertical FET structure Electricity 11 Active
US9318574B2 Method and structure for enabling high aspect ratio sacrificial gates Electricity 11 Active
US9536750B1 Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme Electricity 10 Active
US10304744B1 Inverse tone direct print EUV lithography enabled by selective material deposition Electricity 9 Active
US10074730B2 Forming stacked nanowire semiconductor device Electricity 8 Active
US10014391B2 Vertical transport field effect transistor with precise gate length definition Electricity 8 Active
US9755071B1 Merged gate for vertical transistors Electricity 7 Active
US9728622B1 Dummy gate formation using spacer pull down hardmask Electricity 7 Active
US9425196B1 Multiple threshold voltage FinFETs Electricity 6 Active
US10211316B2 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Electricity 6 Active
US9842739B2 Method and structure for enabling high aspect ratio sacrificial gates Electricity 6 Active
US9331148B1 FinFET device with channel strain Electricity 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.