Method including an adjustment of a plurality of wafer handling elements, system including a plurality of wafer handling elements and photolithography track
US10007198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor processing system that includes a plurality of units. Each unit has a configuration that defines a predetermined orientation of a wafer that is provided in the unit and includes a plurality of wafer handling elements. An arrangement of the plurality of wafer handling elements of the unit relative to the predetermined orientation of the wafer is adjustable. For each of the plurality of units, the arrangement of the plurality of wafer handling elements of the unit is adjusted relative to the predetermined orientation of the wafer. For each of the plurality of units, an arrangement of the plurality of wafer handling elements relative to the predetermined orientation of the wafer is provided that is different from the arrangement of the plurality of wafer handling elements relative to the predetermined orientation of the wafer in one or more other units of the plurality of units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.