Cell current based bit line voltage
US10008273B2 · kind B2 · utility
17Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jul 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.