Method and apparatus for intersymbol interference compensation
US10009197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An intersymbol interference (ISI) compensation circuit includes a data input for receiving an input data signal including a plurality of bits. An adjustment circuit is configured to adjust bit periods of the bits to generate a first adjusted signal and a second adjusted signal. A sampling circuit is configured to generate a first sample signal by sampling the first adjusted signal, and generate a second sample signal by sampling the second adjusted signal. A decision generation circuit is configured to provide a first decision for a first bit. The first decision provides a chosen adjusted signal that is one of the first and second adjusted signals. A selection circuit is configured to determine a compensated value of the first bit based on a chosen sample signal that is one of the first and second sample signals. The chosen sample signal is generated by sampling the chosen adjusted signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.