Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation
US10013519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Nov 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.