Memory system and method for reducing read disturb errors
US10014060B2 · kind B2 · utility
7Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.