Smart skip verify mode for programming a memory device
US10014063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.