Patent · US Active

Method for producing a chip assemblage

US10014275B2 · kind B2 · utility

2Cited by

1References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Alexander Heinrich · Bad Abbach, DE
Irmgard Escher-Poeppel · Regensburg, DE
Martin Gruber · Schwandorf, DE
Andreas Munding · Regensburg, DE
Catharina Wille · Regensburg, DE

Key dates

Filing date	Mar 15, 2017
Grant date	Jul 3, 2018
Priority date	—
Expiry date	Mar 15, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/00014
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.