Bipolar junction transistors with a combined vertical-lateral architecture
US10014397B1 · kind B1 · utility
6Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Dec 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.