Patent · US Active

Method and structure to provide integrated long channel vertical FinFET device

US10014409B1 · kind B1 · utility

7Cited by
0References
9Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 29, 2016
Grant dateJul 3, 2018
Priority date
Expiry dateDec 29, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0142

Abstract

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.