Decoupling arrangement
US10015878B2 · kind B2 · utility
0Cited by
5References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 19, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Nov 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09672
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.