Managing cache coherence using information in a page table
US10019377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.