Arkaprava Basu
19Patents
3h-index
25Co-inventors
56Inventor score
Filing activity: Oct 18, 2011 → Mar 1, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10503658B2 | Page migration with varying granularity | Physics | 8 | Active |
| US10552339B2 | Dynamically adapting mechanism for translation lookaside buffer shootdowns | Physics | 5 | Active |
| US8812786B2 | Dual-granularity state tracking for directory-based cache coherence | Physics | 4 | Active |
| US10282292B2 | Cluster-based migration in a multi-level memory hierarchy | Physics | 3 | Active |
| US9547603B2 | I/O memory management unit providing self invalidated mapping | Physics | 2 | Active |
| US11275613B2 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Emerging Cross-Sectional Technologies | 1 | Active |
| US10078588B2 | Using leases for entries in a translation lookaside buffer | Emerging Cross-Sectional Technologies | 1 | Active |
| US10261916B2 | Adaptive extension of leases for entries in a translation lookaside buffer | Physics | 1 | Active |
| US10019377B2 | Managing cache coherence using information in a page table | Emerging Cross-Sectional Technologies | 0 | Active |
| US10019283B2 | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread | Physics | 0 | Active |
| US11140107B2 | System and method of managing electronic meeting invitations | Physics | 0 | Active |
| US10437736B2 | Single instruction multiple data page table walk scheduling at input output memory management unit | Physics | 0 | Active |
| US12411711B2 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Emerging Cross-Sectional Technologies | 0 | Active |
| US11144473B2 | Quality of service for input/output memory management unit | Physics | 0 | Active |
| US9158704B2 | Virtual memory management system with reduced latency | Physics | 0 | Active |
| US9983655B2 | Method and apparatus for performing inter-lane power management | Emerging Cross-Sectional Technologies | 0 | Active |
| US10592279B2 | Multi-processor apparatus and method of detection and acceleration of lagging tasks | Physics | 0 | Active |
| US10324650B2 | Scoped persistence barriers for non-volatile memories | Physics | 0 | Active |
| US11573724B2 | Scoped persistence barriers for non-volatile memories | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.