Protection from side-channel attacks by varying clock delays
US10019571B2 · kind B2 · utility
1Cited by
38References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, comprising a logic circuit and delay circuitry, is described. The logic circuit is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs. The delay circuitry is configured to vary a power-consumption profile of the logic circuit over the plurality of instances, by applying, to the inputs, respective delays that vary over the instances, at least some of the delays varying independently from each other. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.