Method and structure for minimizing fin reveal variation in FinFET transistor
US10020221B1 · kind B1 · utility
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6References
16Claims
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Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions includes a dielectric layer; and a doped region on the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.