Hao Tang
31Patents
6h-index
44Co-inventors
69Inventor score
Filing activity: May 19, 1994 → Oct 31, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5869845A | Resonant tunneling memory | Physics | 167 | Expired |
| US5930323A | Ultra fast shift register using resonant tunnel diodes | Physics | 24 | Expired |
| US9805983B1 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Electricity | 23 | Active |
| US6507272B1 | Enhanced linearity, low switching perturbation resistor string matrices | Electricity | 14 | Expired |
| US10461174B1 | Vertical field effect transistors with self aligned gate and source/drain contacts | Electricity | 8 | Active |
| US10534276B1 | Lithographic photomask alignment using non-planar alignment structures formed on wafer | Electricity | 6 | Active |
| US10224246B2 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Electricity | 3 | Active |
| US9941150B1 | Method and structure for minimizing fin reveal variation in FinFET transistor | Electricity | 3 | Active |
| US10217658B2 | Method and structure for minimizing fin reveal variation in FinFET transistor | Electricity | 2 | Active |
| US5572626A | Fuzzy membership function generator using resonant tunneling diodes | Emerging Cross-Sectional Technologies | 2 | Expired |
| US10090378B1 | Efficient metal-insulator-metal capacitor | Electricity | 2 | Active |
| US11189566B2 | Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias | Electricity | 1 | Active |
| US11177437B2 | Alignment through topography on intermediate component for memory device patterning | Electricity | 1 | Active |
| US10658589B2 | Alignment through topography on intermediate component for memory device patterning | Electricity | 1 | Active |
| US10651266B2 | Efficient metal-insulator-metal capacitor | Electricity | 1 | Active |
| US11508823B2 | Low capacitance low RC wrap-around-contact | Electricity | 0 | Active |
| US10879190B2 | Patterning integration scheme with trench alignment marks | Electricity | 0 | Active |
| US10020221B1 | Method and structure for minimizing fin reveal variation in FinFET transistor | Electricity | 0 | Active |
| US9678610B2 | Capacitive touch screen and single layer wiring electrode array | Physics | 0 | Active |
| US11543793B2 | Developer critical dimension control with pulse development | Physics | 0 | Active |
| US11022891B2 | Photoresist bridging defect removal by reverse tone weak developer | Physics | 0 | Active |
| US12169348B2 | Anti-glare apparatus and mirror having lens assembly with controlled optical axis direction | Physics | 0 | Active |
| US9768104B1 | Method and structure to fabricate a nanoporous membrane | Electricity | 0 | Active |
| US12111572B2 | Methods of greytone imprint lithography to fabricate optical devices | Physics | 0 | Active |
| US10978550B2 | Efficient metal-insulator-metal capacitor | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.