System, methods and apparatus using virtual appliances in a semiconductor test environment
US10025648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Apr 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/45031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.