Horizontal nanosheet FETs and method of manufacturing the same
US10026652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Nov 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.