Substrate design for semiconductor packages and method of forming same
US10026671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2014 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.