Embedded SiGe process for multi-threshold PMOS transistors

US10026837B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Younsung Choi · Plano, US
• Deborah J. Riley · Sachse, US

Key dates

• Filing date: Sep 3, 2015
• Grant date: Jul 17, 2018
• Expiry date: Sep 3, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.